Multi-level memory cells are widely used as the basic storage units in flash memory. Multi-level memory cells are capable of storing four different cell levels corresponding to two bits. Programming the states of a multi-level memory cell is a two phase process, in which the least significant bit page is written, putting the cells into an intermediate state reflecting the value of the least significant bit. Next the noisy least significant bit page is read before both the least significant bit and most significant bit pages are written, putting the cells in the final target states before the next erase. The least significant bit and most significant bit are written independently to maintain high write/read throughput; the least significant bit page is not stored after writing to flash because the most significant bit page might not be available immediately afterwards for writing. The most significant bit page is written based on the read least significant bit page, without passing the least significant bit through an error correcting code first; therefore the final programmed state maybe in error because of the rough distribution of the intermediate state ‘x0’, where the left tail of the distribution intersects with state ‘11’ after many program/erase cycles, or after significant data retention. The least significant bit read process affects write throughput, and so is latency critical; therefore the noisy least significant bit read is not corrected before writing the final state.
Consequently, it would be advantageous if an apparatus existed that is suitable for reliably distinguishing the intermediate and erase cell states after many program/erase cycles, read cycles, or long data retention.